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Adding external SRAM to the Atmega128L+EM2420

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Applications requiring additional SRAM on the EM2420 platform can use the memory bus available on the Atmega128L to easily access this RAM from the embedded software. This HOWTO explains how to connect everything and configure the IAR compiler and HAL software to do this.

Adding external RAM can be done with very little software modification because the extra memory is treated like a continued portion of the existing internal memory.

See the section called "SRAM Data Memory" in the "AVR ATmega128 Memories" chapter of the ATmega128 datasheet (available here: http://www.atmel.com/dyn/products/datasheets.asp?family_id=607).

The hardware must be modified as per the guidelines in the "External Memory Interface" section of this same chapter, which explain how to use the Atmega's dedicated External Memory pins.

IAR project changes for using extended memory ("XMEM")

  • In XLINK, #define tab, change the following defined symbols to correspond to your XMEM setup:

_..X_EXT_SRAM_BASE=1100 <-- This is always the starting address of the XMEM segment
_..X_EXT_SRAM_END=90FF <-- This should allow for at least as much space as your XMEM address mask provides for (depends on how much XMEM you plan to use). 0x90FF will be the end of the first XMEM sector (~28KB) as set by XMCRA and allows for enough addressing for 32KB (+4KB internal). If using 64KB of XMEM, you should choose "FFFF" for this value instead.

  • In ICCAVR, Extra options tab, add the following option to compile with external data bus support:
--enable_external_bus

  • If using an extended SRAM configuration with >32KB XMEM: When loading bootloader to your devices, make sure to use the bootloader with "noLED" in the name, so that the LED pins (PC2-PC7) are not triggered during Bootloader activity (since these pins are used for the highest bits of the address bus).

Code additions for adding XMEM capabilities to HAL

In your BOARD_HEADER file for the hardware, either in the halInternalPowerUpBoard(), or in another initialization routine for your device, add the following:

  1. /**
  2. Turns on SRAM Enable (SRE);
  3. PG0 - PG2 pins become nRD, nWR, and ALE pins now;
  4. data direction is now under control of the XMEM interface
  5. **/
  6. MCUCR |= BIT(SRE); 
  7. /**
  8. Set XMEM ctrl reg A for wait-state timing of diff. XMEM sectors;
  9. 0 is default, where all XMEM is one sector with same read/write timing for every address;
  10. can alter these for XMEM segmentation and timing;
  11. see ATmega128 datasheet, Tables 3 &amp; 4, Page 30. 
  12. **/
  13. XMCRA = 0; 
  14. /**
  15. Set XMEM ctrl reg B for XMEM bus-keeper and address mask;
  16. 0 is default, where bus-keeper is disabled and address mask allows up to 
  17. 60k SRAM, no PCx pins available;
  18. Can alter these to limit XMEM and reclaim Port C pins 
  19. (Ember uses these for LEDs); 
  20. See ATmega128 datasheet, Table 5, Page 31. 
  21. **/
  22. XMCRB = 0; 




Hardware

Attached to this HOWTO is a portion of a
schematic for a hardware design using external SRAM.  The page enclosed
shows the ATmega128L connections (including external SRAM, which is
mostly in the upper-righthand quandrant of the schematic).  To help
explain the pieces used in the schematic, below is a list of components
for the board that are involved in the SRAM connections:

  • U1 = IC, LOW VOLTAGE OCTAL D-TYPE LATCH, TSSOP-20
	(Toshiba TC74LCX573FT, rated for operating temps -40 to +85 degrees C;
	see http://www.toshiba.com)
    • 
	
  • U2 = IC, 32K X 8
	LOW VOLTAGE STATIC RAM, TSOP-28 (Integrated Silicon Solutions Inc.
	[ISSI.com] IS62LV256-70T, about 72 cents/ea; rated for operating temps
	0-70 degrees C, but "industrial" version is also available with -40 to
	+85 temp rate; see www.issi.com) Note: These are measured in words
	rather than bytes, so 32K X 8 means 32K words (at 2 words per byte) x 8
	bits per byte, for 64K total SRAM.
    • 
	
  • C1, C2: CAP,10NF,+/-10%,25V,X7R,0402 SMT (basic 10nF, surface-mount capacitor)
    •